Front-End Wafer Processing & Handling
In semiconductor device fabrication, the various processing steps fall into four general categories: Deposition, Removal, Patterning, and Modification of electrical properties.
Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies consist of Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Electrochemical Deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others.
Removal processes are any that remove material from the wafer either in bulk or selectively and consist primarily of etch processes, either wet etching or dry etching. Chemical-Mechanical Planarization (CMP) is also a removal process used between levels.
Patterning covers the series of processes that shape or alter the existing shape of the deposited materials and is generally referred to as lithography. For example, in conventional lithography, the wafer is coated with a chemical called a photoresist. The photoresist is exposed by a stepper, a machine that focuses, aligns, and moves the mask, exposing select portions of the wafer to short wavelength light. The exposed regions are washed away by a developer solution. After etching or other processing, the remaining photoresist is removed by plasma ashing.
Modification of electrical properties has historically consisted of doping transistor sources and drains originally by diffusion furnaces and later by ion implantation. These doping processes are followed by furnace anneal or in advanced devices, by rapid thermal anneal (RTA) which serve to activate the implanted dopants. Modification of electrical properties now also extends to reduction of dielectric constant in low-k insulating materials via exposure to ultraviolet light in UV processing (UVP).
Wet Bench & Clean Room
Since 1984, Professional Plastics has been supplying the widest variety of premium, corrosion-resistant plastic materials to the semiconductor industry. "Wet Benches" are stations for wet etching and cleaning of wafers and devices. The various wet benches differ in the specific process modules available and the materials allowed at each station. The general use wet bench is for acid or base processing of non-standard materials. Semi-automated wet etch bench, primarily for stripping photoresist, removing scribe dust and wet oxide etching. Semiconductor processing and cleanroom equipment include; Automated wet benches, Semi-automated wet benches, Wet process systems, Cleanroom equipment and furniture, Fume hoods, Quick rinse stations, Spin rinser dryers, Wet etch processing equipment, Chemical distribution cabinets, Wet process systems, Chemical handling equipment, Laminar Flow Work Systems & Hoods, Chemical Delivery Carts, Acid Processing Stations, Chemical Fluid Lines and Quick Dump Rinsers.
Back-End IC Fabrication & Testing is where the individual devices (transistors, capacitors, resistors, etc.) get interconnected with wiring on the wafer. This generally begins when the first layer of metal is deposited on the wafer. BEOL includes contacts, insulating layers, metal levels, and bonding sites for chip-to-package connections. Wafer Test metrology equipment is used to verify that the wafers haven't been damaged by previous processing steps up until testing. If the number of diesâÇ"the integrated circuits that will eventually become chipsâÇ" etched on a wafer exceeds a failure threshold (i.e. too many failed dies on one wafer), the wafer is scrapped rather than investing in further processing.
Device Test involves subjecting the semiconductor devices to a variety of electrical tests to determine if they function properly. The proportion of devices on the wafer found to perform properly is referred to as the yield. Manufacturers are typically secretive about their yields, but it can be as low as 30%. Probe Testing involves testing the chips on the wafer with an electronic tester that presses tiny probes against the chip. Chips are also tested again after packaging, as the bond wires may be missing, or analog performance may be altered by the package. This is referred to as "final test".
Wafer Testing is a step performed during semiconductor device fabrication. During this step, performed before a wafer is sent to die preparation, all individual integrated circuits that are present on the wafer are tested for functional defects by applying special test patterns to them. The wafer testing is performed by a piece of test equipment called a wafer prober. The process of wafer testing can be referred to in several ways: Wafer Sort (WS), Wafer Final Test (WFT), Electronic Die Sort (EDS) and Circuit Probe (CP) are probably the most common.
A Wafer Prober is a machine used to test integrated circuits. For electrical testing a set of microscopic contacts or probes called a probe card are held in place while the wafer, vacuum-mounted on a wafer chuck, is moved into electrical contact. When a die (or array of dice) have been electrically tested the prober moves the wafer to the next die (or array) and the next test can start. The wafer prober is usually responsible for loading and unloading the wafers from their carrier (or cassette) and is equipped with automatic pattern recognition optics capable of aligning the wafer with sufficient accuracy to ensure accurate registration between the contact pads on the wafer and the tips of the probes.